The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, is neither expressly nor impliedly admitted as prior art against the present disclosure.
Typically, performing storage device operations requires the central processing unit (CPU) to play a key role until the operations are complete. This reduces bandwidth on the bus between the CPU and the storage device because data must continuously be transferred between the storage device and the CPU over the bus. For example, to perform a move operation for a large data set in a storage device, the CPU needs to read each piece of information from one storage location and then write the information to another storage location. Each read and write of the information requires the data to be communicated through the bus between the CPU and the storage device. In addition, because the CPU is heavily involved in the memory operations, the capacity of the CPU is reduced for taking on other tasks.